Modeling Logic Gates and Circuits with Generalized Nets

Abstract

In this paper, modeling of logic gates is presented for the first time. Four models of Generalized Nets (GN)—AND gate, a binary to decimal decoder, delay type flip-flop, n-bit binary counter and logical circuits are presented in the following paper. Here we also suggest using the recently proposed approach of InterCriteria Analysis, based on index matrices and intuitionistic fuzzy sets, which aim to detect possible correlations between pairs of criteria. We can perform the measurements, if we have a set of several logical circuits that can be used to obtain identical output data. The aforementioned logical circuits must be composed of different logical elements. By using several measurement points and different schematics, we can suggest the best solution for the considered type of task.