Abstract

This paper is a continuation of the previous two papers [7, 8], representing generalized net model of one of the major binary counter types – a synchronous binary counter. We can perform the measurements, if we have a set of several logic circuits that can be used to obtain identical output data. These logic circuits must be composed of different logic elements. By using several measurement points and different schematics, we can infer the best solution for the considered type of task.

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