Abstract
This paper is a continuation of the previous two papers [7, 8], representing generalized net models of two of the basic sequential logic circuits - SR and JK flip-flop circuits. We can perform the measurements, if we have a set of several logical circuits that can be used to obtain identical output data. The aforementioned logical circuits must be composed of different logical elements. By using several measurement points and different schematics, we can infer the best solution for the considered type of task.
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