Modeling Junctionless Metal-Oxide-Semiconductor Field-Effect Transistor

Abstract

Metal-oxide semiconductor (MOS) field-effect transistor (FET) scaling is following the prediction of the Moore's law for the past 45 years, a key factor that enabled the IC industry to cope with the everlasting demand for higher performances. However, this scaling process becomes increasingly difficult as several limits from both process and device capabilities pop up as the technology node reaches 28nm and beyond. To stand the pace of downscaling, non-classical devices are currently introduced in the roadmap. In this context, the junctionless FET is part of these attempts. It is a new emerging device that can potentially withstand the downscaling of CMOS technology as it still has an excellent control from the gate, a low leakage current, an expected enhancement in carrier transport, besides easier fabrication processes. This dissertation focuses on the physics and modeling of nanoscale junctionless double-gate MOSFET and junctionless nanowire FETs. The first part of the thesis is focusing on junctionless transistors by discussing the advantages and limitations of such technology. A brief overview of existing models and the current status of symmetrical/asymmetrical operation of junctionless FETs in a planar double-gate configuration as well as junctionless nanowires topologies will be presented. Next, the model that is developed in this thesis is detailed in different chapter, each of which will cover a specific aspect. The model relies on Poisson-Boltzmann equation and on the drift-diffusion transport to derive charges and current in long-channel devices. It is based on two set of relationships to cover all the operating regions: from depletion to accumulation; from linear to saturation with no fitting parameter. Following a core analysis, more features are developed and added to the ideal long-channel concept. This includes modeling short-channel effects and DIBL, modeling full trans-capacitance matrix for AC simulations, modeling thermal noise and induced gate noise, modeling the inversion layer to predict off-state currents. Importantly, we have shown that equivalent symmetric devices could also be used to simulate asymmetric operation, which are likely to be the most common situation. In addition, the charge-based approach developed along the thesis has also been generalized to the quite popular junctionless nanowire architecture. Regarding junctionless FETs, technological parameter are very critical. For instance, the device cannot be made of any dimension and doping otherwise it cannot be effectively switched off at a given current. Therefore, we also derived rules providing a design-space tool with explicit links between silicon thickness and doping ensuring safe operation. Finally, since the mobility extraction in junctionless FETs is still an issue, we have developed a new method for a reliable measurement of free carriers mobility in real devices which does not assume any predefined mobility law. Based on these developments, the EPFL-JL-model was implemented into Hspice platforms to be used by circuit designers.