Modeling and TCAD Assessment for Gate Material and Gate Dielectric Engineered TFET Architectures: Circuit-Level Investigation for Digital Applications

Abstract

This paper deals with the development of a generalized model describing the device electrostatic behavior of three different double gate n-type tunnel FET (TFET) architectures, i.e., dual material gate (DMG) TFET, heterodielectric (H-D) TFET, and dual material gate heterodielectric (DMG H-D). The model is advantageous in capturing the impact of dielectric and the metal gate length variation where a comparative study among these three aforementioned device architectures has been made in terms of various electrostatic parameters, such as surface potential, energy-band profile, and electric field, incorporating the impact of interface oxide charges. Subsequently, TCAD-based digital performance investigation for all these architectures has been performed where their capacitive behavior and the transient performance has been carefully analyzed and optimized by varying the metal work function (M <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ) and length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ) value for both, i.e., the dielectric material and the metal gate. Both the modeling and simulation results reveal that the proposed architecture, i.e., DMG H-D TFET, outperforms the other two architectures, i.e., DMG and H-D TFET.