Abstract
This paper presents a technique for the modeling and design of a nano scale CMOS inverter circuit using artificial neural network and particle swarm optimization algorithm such that the switching characteristics of the circuit is symmetric, that is, has nearly equal rise and fall time and equal output high‐to‐low and low‐to‐high propagation delay. The channel width of the transistors and the load capacitor value are taken as design parameters. The designed circuit has been implemented at the transistor‐level and simulated using TSPICE for 45 nm process technology. The PSO‐generated results have been compared with SPICE results. A very good accuracy has been achieved. In addition, the advantage of the present approach over an existing approach for the same purpose has been demonstrated through simulation results.
Highlights
For digital integrated circuit design, CMOS inverter design is considered to be a fundamental procedure [1]
This paper presents an approach for the design of a nano scale CMOS inverter circuit with symmetric switching characteristics
The input design parameters of the Artificial neural network (ANN) model are the widths of the PMOS and NMOS transistor, the load capacitor and the rise time of the input signal
Summary
For digital integrated circuit design, CMOS inverter design is considered to be a fundamental procedure [1]. In the nano scale regime, the task of manual design of an optimal integrated circuit is very difficult. The performance behaviours of a circuit in this regime depend on the transistor channel length and width through complex high orders of equations. For correct design and simulation of nano scale digital integrated circuits, accurate models need to be constructed [2]. The construction of accurate performance model for CMOS inverter valid in the sub-90 nm domain is, an important problem to be solved. The design of an inverter circuit for optimized performance is considered as a nonlinear optimization problem
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