Abstract

Field Emission Scanning Probe Lithography (FE-SPL) is an enabling technology for prototyping of sub-10 nm high-performance electronic devices. However, due to the serial writing scheme this technology is rather slow. The purpose of this work is the demonstration of a mix-and-match process in combination with cryogenic etching in order to fabricate templates for Nanoimprint Lithography (NIL). We describe (i) the fabrication of a micron-sized electrode layout on a 1.5 mm × 1.5 mm area by means of fast Direct Laser Writing (DLW), (ii) the subsequent stitching of nano-sized features on the same resist layer using high-resolution FE-SPL and (iii) the pattern transfer into silicon. IC manufacturing requires both, large throughputs with critical feature size smaller than 5 nm. Therefore, the motivation of our project is to develop a lithographic process for nano-electronic devices with critical feature size smaller than 5 nm, while the rest of the device sizes are 100 nm or larger. Thus, a possible SET template was designed for future high-throughput NIL.

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