Mitigating Soft Error Rate Through Selective Replication in Hybrid Architecture

Abstract

With the rapid development of integrated circuit technology, soft error has increasingly become the major factor for the reliability of microprocessors. The researchers employ a variety of methods to reduce the influence of soft errors. Besides the lower delay and increasing bandwidth, 3D integration technology also has the ability of heterogeneous integration. STT-RAM is a new storage technology with broad prospects. The characteristic that STT-RAM is immune to soft errors makes it ideal candidate for improving reliability and STT-RAM can be integrated into the 3D chip through heterogeneous integration. In this paper, we proposed a selective replication mechanism for soft error rate reduction in hybrid reorder buffer architecture based on the 3D integration technology and STT-RAM. Instructions will be replicated or migrated to STT-RAM for reliability improvement in certain situations. The experimental results show that the soft error rate of the proposed hybrid structure is reduced by 15 % on average and the AVF decreased 54.3 % further on average through the in-buffer selective replication mechanism while the performance penalty is 2.8 %.