Improved access pattern for ROB soft error rate mitigation based on 3D integration technology

Abstract

With the progress of integrated circuit technology, the soft error problem has become more and more serious, which has become a real challenge for reliability design. 3D integrated technology, which is capable of stacking multi circuit layers in the vertical direction, offers the shielding effect to reduce the probability of soft errors. In this paper, we focus on reorder buffer(ROB), and conduct a fine-grained analysis of the AVF of each ROB entry. Based on the non-uniformity of AVF, the ROB is divided into two parts, which statically layout to different circuit layers in 3D chip. Based on the observation that ROB occupancy rate is low at most of the time, we propose a dynamic mapping access pattern and a migration access pattern further to reduce the soft error rate. Simulation results show that the soft error rate was reduced by 47.6%, 84.5% and 88.2% respectively, with the static layout, dynamic mapping and migration access patterns. Considering the correlation analysis on the soft error rate and the capacity of ROB, a better balance between the soft error rate reduction and the area overhead can be achieved if the capacity is 80.