MISC

Abstract

This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC architecture uses multiple asynchronous processing elements to separate a program into streams that can be executed in parallel, and integrates a conflict-fne message passing system into the lowest level of the processor design to facilitate low latency intraMISC communication. This approach allows for increased machine parallelism with minimal code expansion, and provides an alternative approach to single instruction stream multi-issue machines such as SuperScalar and VLIW. 1. The MISC Design The MISC processor, a direct descendant of the PIPE project [CGKP87,GHLP85] will exploit both the instruction and data parallelism available in a task by combining the capabilities of traditional data parallel architectures with those found in machines designed to exploit instruction level parallelism. Unlike the two pm cessor PIPE design, the MISC system is capable of balancing the processor load of instructions performing memory access and execute operations among four processors. The characteristics of the MISC design also allow the introduction of a number of new and unique instructions, like the Sentinel and Vector instructions described later in this paper. As its name indicates, MISC is composed of multiple Processing Elements (PES) which cooperate in the execution of a task. MIX