Abstract
This paper proposes a new micro-architecture, called IAS-S, which takes advantage of the Conjugate Register File (CRF) scheme to support speculative execution, such as multi-level boosting and multi-way branch, without incurring excessive hardware overhead. A software technique which integrates register allocation and instruction scheduling has been developed to exploit the conjugate register file. The scheduling-conflict graph is built before the starting of register allocation so that the ability of the instruction scheduler to optimize the instruction sequence will not be severely restricted by the reuse of registers.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.