Minimizing the energy-delay product of SRAM arrays using a device-circuit-architecture co-optimization framework

Abstract

The objective of this paper is to minimize the energy-delay product of static random access memory (SRAM) arrays by using a device-circuit-architecture co-optimization framework. More specifically, at the device-level, high-V t FinFETs are adopted for the 6T SRAM cell, which significantly reduces the leakage power and improves static noise margins. However, due to the lower ON current, the bitline delay of the read access is increased. Accordingly, at the circuit-level, the voltage level of assist circuits, and at the architecture-level (i.e., the array organization), key parameters of the SRAM array are jointly optimized to derive a design that results in the minimum energy-delay product point. By using the proposed optimization framework, for SRAM array capacities ranging from 1KB to 16KB, on average 59% lower energy-delay product with maximum 12% (and on average 9%) performance penalty is achieved.