Design of SRAM array using 8T cell for low power sensor network

Abstract

The application of sensor networks varies from medical field to the military application. The raw data onto the sensor node is of large quantity and it is necessary to store these data bits. In this paper, design of optimized Static Random Access Memory (SRAM) array for the sensor application is implemented. SRAM cell is designed using 8T. The Half Select Condition Free Cross Point 8T SRAM is modified, using transmission gates as access transistors. By simulation, it is observed that the write-ability is enhanced and reduction in the power dissipation. Apart from the memory cell, the SRAM array has been constructed using the optimized peripheral circuits. Simulations show that reading and writing of data takes place correctly.