Abstract
The VAX Architecture provides hardware implementors with an opportunity or a nightmare, depending on your point of view. Such characteristics as 304 opcodes, a large number of addressing modes, a large number of supported data types, and non-regularities in the ISA semantics all provide challenges to the microarchitect. The VAX architecture was introduced in 1977 with its first microarchitecture, the VAX 11/780, a TTL MSI implementation. Since then, there have been several distinct implementations, each reflecting (1) the technology in which it was implemented, (2) the performance/cost tradeoffs it was supposed to consider, and (3) the design methodology of its implementors. This paper is a first attempt at discussing several VAX implementations from the standpoint of the choices made in the microarchitecture as driven by the context of the device technology, the performance/cost tradeoffs, and other considerations.
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