Metrology Challenges for 45-nm Strained-Si Device Technology

Abstract

The semiconductor industry has maintained its historical exponential improvement in performance by aggressively scaling transistor dimensions. However, as devices approach sub-100-nm dimensions, scaling becomes more challenging and new materials are required to overcome the fundamental physical limitations imposed by existing materials. For example, as power supply voltages continue to decrease with successive scaling, enhancing carrier mobility using biaxially tensile-stressed Si on relaxed SiGe on SOI and on bulk substrates has become a viable option to sustain continual drive current increase without traditional scaling. Although the addition of strained-Si to conventional MOSFET devices is compatible with existing mainstream CMOS process technology, there are new device and process integration challenges, wafer quality monitoring demands, and stringent requirements for film morphology and strain uniformity, imposing new demands on material characterization. Material requirements for strained-Si CMOS devices include having uniform SiGe thickness, Ge composition, and strain distribution. These are required to maintain uniform device performance as well as low defect density for high minority carrier lifetimes and transconductance, as well as low surface roughness to minimize the impact of interface scattering on carrier mobilities. The parameters of interest in strained-Si CMOS technology include SiGe and Si channel thickness, Ge composition, strain, dislocation density, interface quality, and roughness. Nondestructive inline metrology techniques include spectroscopic ellipsometry for film thickness and Ge composition, X-ray reflectivity for thickness, density, and roughness measurements, X-ray fluorescence for Ge composition, UV-Raman spectroscopy for channel strain characterization, IR photoluminescence for defect detection, and X-ray diffraction for both Ge content and strain measurement. While most of these techniques are well established in the semiconductor industry, some will require development for application to volume manufacturing. This paper will focus on various metrology approaches used in strained-Si CMOS devices