Metrology Challenges for 45 nm Strained-Si Devices

Abstract

The semiconductor industry has sustained its historical exponential performance gains by aggressively scaling transistor dimensions. However, as devices approach sub‐100 nm dimensions, scaling becomes more challenging and new materials are required to overcome the fundamental physical limits imposed by existing materials. For example, as power supply voltages continue to decrease with successive scaling, enhanced carrier mobility using biaxially tensile‐strained‐Si on SOI or on bulk substrates have become viable options to sustain continual drive current increases without traditional scaling. Although the addition of strained‐Si to conventional MOSFET devices is compatible with existing mainstream CMOS process technology, there are new device and process integration challenges, wafer quality monitoring demands, and stringent requirements for film morphology and strain uniformity, imposing new demands on material characterization. Material requirements for strained‐Si CMOS devices include homogeneous Si or SiGe film thickness, Ge composition, strain distribution to maintain uniform device performance. Also important are having good interface quality and low defect density (misfit and threading dislocation densities below 1e4/cm2) to ensure high minority carrier lifetimes and transconductance, and low surface roughness (<3A RMS) to minimize the impact of interface scattering on carrier mobilities. Non‐destructive, in‐line metrology techniques include spectroscopic ellipsometry (SE) for film thickness and Ge composition, xray reflectivity (XRR) for thickness, density, and roughness measurements, xray fluorescence (XRF) for Ge composition, UV‐Raman spectroscopy for channel strain characterization, IR photoluminescence (PL) for defect detection, and xray diffraction (XRD) for film thickness, Ge content, and strain measurement. While most of these techniques are well established in the semiconductor industry, some will require performance enhancements and development for application to volume manufacturing. For example, as wafer test areas continue to shrink, spot sizes must also be reduced. It also becomes more difficult to extend measurements made on large test areas to small device features.The semiconductor industry has sustained its historical exponential performance gains by aggressively scaling transistor dimensions. However, as devices approach sub‐100 nm dimensions, scaling becomes more challenging and new materials are required to overcome the fundamental physical limits imposed by existing materials. For example, as power supply voltages continue to decrease with successive scaling, enhanced carrier mobility using biaxially tensile‐strained‐Si on SOI or on bulk substrates have become viable options to sustain continual drive current increases without traditional scaling. Although the addition of strained‐Si to conventional MOSFET devices is compatible with existing mainstream CMOS process technology, there are new device and process integration challenges, wafer quality monitoring demands, and stringent requirements for film morphology and strain uniformity, imposing new demands on material characterization. Material requirements for strained‐Si CMOS devices include homogeneous Si or...