Methods to Enhance the Performance of InGaAs/InP Heterojunction Tunnel FETs

Abstract

This paper presents a simulation study of In0.53Ga0.47As/InP heterojunction gate-overlapped-source tunnel FETs (GoS-TFETs) with pocket counter-doping. The effect of channel quantization on the line tunneling is considered in the semiclassical simulations using a new model that modifies the band edge in the inversion layer. The small bandgap of the source material In0.53Ga0.47As results in an improved tunnel rate, while the wide bandgap of the channel/drain material InP reduces ambipolar leakage. The simulations show that, for the case of perfectly aligned p-n-junction and heterojunction, the type-I band alignment and the large band offsets delay suppress lateral (point) tunneling relative to vertical (line) tunneling which improves the subthreshold swing (SS). The counter-doped pocket in the source region advances the onset of line tunneling relative to point tunneling which also assists in mitigating the effects of point tunneling. In this way, both large band offset and counter-doped pocket improve the subthreshold behavior of the TFET. Placing the p-n-junction inside the InP region makes the vertical tunneling even more dominant and, thus, reduces the SS. The suggested modifications might be useful to improve the device performance beyond that of the conventional GoS-TFETs.