Analysis of heterojunction GaAs1−xSbx/In1−yGayAs tunnel FETs considering line tunneling

Abstract

In this work, we analyze the heterojunction GaAsi-xSbx/Ini-yGayAs Tunnel FETs (TFETs) with various material compositions and effective tunneling barriers (E beff ) considering line tunneling. An epitaxial channel layer is placed between source and gate dielectric (TFET with T epi ) to introduce the line tunneling which increases the on current significantly compared with the conventional p-i-n TFET with point tunneling only. The current components of TFET with T epi consist of both vertical line tunneling and lateral point tunneling. The onset voltage of line tunneling is defined as the gate voltage at which the drain current is dominated by line tunneling. The onset voltage of line tunneling can be reduced as E beff decreases. Therefore, for TFET with T epi and smaller E beff , the on current improvements owing to the increased gate-to-source overlap length (Lovs) are more significant than that with larger E beff . As Lovs increases, the drain currents contributed by vertical line tunneling are enhanced due to the increased tunneling area, while the drain currents contributed by lateral point tunneling are suppressed due to the increased tunneling width. Heterojunction GaAs 1−x Sb x /In 1−y Ga y As TFET with T epi should be designed with smaller E beff to gain advantage of line tunneling.