Device Designs of III-V Tunnel FETs for Performance Enhancements through Line Tunneling

Abstract

In this paper, we analyze the device designs of III-V TFET with line tunneling for on current and average subthreshold swing enhancements. Compared to the conventional TFET with point tunneling, TFET with an epitaxial channel layer between gate and source introduces line tunneling. The onset voltage of line tunneling depends on the effective tunneling barrier (Eb eff ) and the thickness of epitaxial layer (T epi ). TFET with larger Eb eff shows larger onset voltage of line tunneling which degrades the average subthreshold swing. Compared with thick T epi , GaAs 0.4 Sb 0.6 /In 0.65 Ga 0.35 As TFET with thin T epi exhibits lower drain current at V}_{g}}=0.1V} while larger I on at V}_{g}}=0.5V}. For TFET with T epi and line tunneling, T epi should be optimized to obtain high I on and low average subthreshold swing. GaAs 0.4 Sb 0.6 /In 0.65 Ga 0.35 As TFET with T}_{epi}}=2nm} and 10nm gate-to-source overlap length (L ovs ) shows 3.3X higher I on (406μ A}/μ m}) and lower subthreshold swing (20.67mV/dec) than the conventional TFET. Thinner source-to-channel lateral junction thickness (T S ) and larger gate-to-drain underlap length (L und ) decrease the I off and improve the subthreshold swing.