Metastability analysis of CMOS current mode logic latches

Abstract

This paper presents a detailed analysis of metastable behavior in CMOS current mode logic (CML) latches. The variation of the latch delay is primarily caused by the finite current transition time, which in fact depends on the rise/fall times of the clock signal. In this analysis a relation is defined between the latch characteristic parameters and the signal slew rates. The presented analysis is specific for CML latches, but it still gives insight of such behavior in other latch and flip-flop structures. 0.18 mum CMOS technology examples are provided