An improved high speed, and low voltage CMOS current mode logic latch

Abstract

A high-speed, low voltage CMOS current mode logic (CML) latch, that has high input, and output voltage dynamic ranges, is proposed in this paper. The input common-mode voltage, and the output voltage dynamic range behavior are analyzed for the proposed latch and the most common (or typical) latch. Both CML latch structures were designed in a 0.18 $$\upmu$$μm RFCMOS technology with a nominal voltage $$V_{DD}=1.8$$VDD=1.8 V. The output voltage errors, which the main cause is due to input voltage variations, even when the circuit is in latch mode, are analyzed in this paper. The post-layout results, using a clock frequency at 10 GHz, and the same bias current of 6 mA for both circuits shows an increment of 60 % for the output voltage swing in the proposed latch versus the typical latch. Besides, this topology being more robust it can be used for higher frequencies up to 20 GHz.