Abstract
Intrinsic gate-capacitance characteristics of long-channel SOI MOSFETs are investigated by measurements up to 300°C and by two-dimensional simulations up to 400°C. Room temperature particularities related to impact ionization and floating body are successfully reproduced by a.c. simulations. Transient simulations are used in order to gain a deep physical insight into the observed phenomena. The contribution of majority carriers generated by impact ionization or back accumulation is clearly established. At high temperature, differences with room temperature behavior observed above and below threshold voltage are explained in terms of thermally generated excess carriers and impact ionization reduction. The analyzed features are the threshold voltage, the subthreshold slope, and particular humps near threshold and subthreshold capacitance values. Implications for analog or digital circuit operation are briefly discussed.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
