A compact capacitive approach based threshold voltage modeling and performance comparison of a novel UBR MOSFET with SOI MOSFET

Abstract

In our present work, we have investigated a newly introduced metal oxide semiconductor field effect transistor with an undoped buried region (UBR) just beneath the channel and a buried oxide layer only under the source and the drain regions. A compact capacitive approach has been followed to develop a threshold voltage model of the said UBR MOSFET structure. Depending on this threshold model, an overall performance comparison of the UBR MOSFET has been carried out with its Silicon-on-Insulator (SOI) MOSFET equivalent in terms of threshold voltage roll-off and sub-threshold slope to establish the superiority of the novel UBR MOSFET over its SOI counterpart. The threshold voltage is seen to be lower in the UBR MOSFET than that of the SOI MOSFET, resulting in an increased current driving capability and higher switching speed of the said UBR device. The lower threshold voltage roll-off, self-heating effect and sub-threshold slope indicates the comparatively reduced impact of short channel effects in the case of UBR MOSFET than the corresponding SOI device thereby providing ample scope for further device miniaturization and significant performance improvement, making it a potential candidate for high temperature ultra low dimensional circuits.