Measurement and Simulation Methods for Assessing SRAM Reliability Against Random Telegraph Noise

Abstract

In this chapter, methods for statistically characterizing and estimating the impact of random telegraph noise (RTN) on static random access memory (SRAM) reliability are described. RTN refers to random transition between two conduction states of a transistor with time, associated with trapping/de-trapping of a single electron or hole. It is a reliability concern for advanced integrated circuits using extremely small transistors, since their electrical characteristics can be significantly altered by only a single elementary charge carrier, which may lead to circuit malfunction. One thing that makes RTN characterization difficult is its statistical nature, as both the existing number of charge traps in a transistor as well as signal amplitude and time constants associated with each trap will vary from one transistor to another. In addition, the time constants are distributed over several orders, and may be unpredictably long. To address this matter, RTN characterization using SRAM arrays was proposed, where a large number of SRAM malfunction events by RTN are recorded and statistically analyzed. A method of fast Monte Carlo simulation was also proposed, which can be conveniently used in combination with the SRAM measurements. The information thus obtained can be used to properly design SRAM cells, as well as their shipment tests, so that the probability of malfunction is suppressed to an acceptable level.