Abstract
The existing Berkeley neutron sensitiveMCP/Timepix hybrid detector has been very successful at demonstratingenergy resolved spatial imaging with a single Timepix ASIC read out ata ∼ 30 Hz frame rate where each neutron's positionand time (energy) is determined (X,Y,E). By increasing the detectorformat using a quad arrangement of Timepix readouts and increasing theframe rate to 1 kHz, we can increase our total event throughput by afactor of 120, thereby taking full advantage of the high fluxes ofmodern pulsed neutron sources (106 ncm−2 s−1). The key to thisconversion is a new design for the ASIC readout, called the BerkeleyQuad Timepix detector, consisting of 3 major subsystems. The first is aquad (2 × 2) bare Timepix ASIC board mounted directly behind the neutronsensitive MCPs in a hermetic vacuum enclosure with a sapphire window.The data from the Timepix ASICs flow to the second subsystem called theInterface board whose field programmable gate array (FPGA) rearrangesand converts the digital bit stream to LVDS logic levels before sendingdownstream to the third subsystem, the Roach board. The Roach board isalso FPGA based, and takes the data from all the ASICs and analyses theframes to extract information on the input events to pass on to thehost PC. This paper describes in detail the hardware and firmwaredesigns to accomplish this task.
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