Design and implementation of digital Costas loop and Bit synchronizer in FPGA for BPSK demodulation

Abstract

This paper describes the design and implementation of digital Costas loop for carrier recovery and demodulation of the data with Bit synchronizer for clock recovery in Field Programmable Gate Array (FPGA) for Binary Phase Shift Keying (BPSK) demodulation. For coherent demodulation, synchronization system is essential to extract carrier frequency and phase information from the received signal. The classical BPSK demodulation technique is the Costas loop, which can be either analog or digital that obtains the phase and frequency information of the modulated carrier as well as demodulates the data. In analog Costas loop, an imbalance between the in-phase and quadrature-phase exists which requires fine tuning. To overcome this problem of analog design, digital design is used. The digital implementation in a Digital Signal Processor (DSP) or FPGA is beneficial in terms of size, complexity and it is also tunable. In the present invention, the whole system is implemented in a single FPGA. The early-late gate technique is used for the design of Bit Synchronizer. The digital system design is simulated in MATLAB and the VHDL code developed in ACTEL LIBERO software is simulated in ModelSim simulator. Finally, the whole system is implemented in ACTEL PROASIC3E FPGA. The major advantages of the system include reprogrammablility, repeatability, reduced cost and low power consumption with less hardware.