Abstract
This paper focuses on the maximum peak shifting phenomenon observed in drain-source voltage proflle during the turn-off transient of Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor (SiC MOSFET). The cause of this phenomenon is identified and discussed. The influence of power loop parasitic resistance and common source inductance on voltage overshoot and ringing is also analyzed. Both large power loop parasitic resistance and common source inductance lead to damping of voltage ringing as well as peak growth. Peak growth becomes a concern under two conditions; prolonged turn-off transient and a high ratio of common source inductance to power loop inductance. Both of these can make the maximum voltage peak grow beyond the safe operation area (SOA) of SiC MOSFET.
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