Materials Requirements of High-Speed and Low-Power Spin-Orbit-Torque Magnetic Random-Access Memory

Abstract

As spin-orbit-torque magnetic random-access memory (SOT-MRAM) is gathering great interest as the next-generation low-power and high-speed on-chip cache memory applications, it is critical to analyze the magnetic tunnel junction (MTJ) properties needed to achieve sub-ns, and ~fJ write operation when integrated with CMOS access transistors. In this paper, a 2T-1MTJ cell-level modeling framework suggests that large spin Hall conductivity and moderate SOT material sheet resistance are preferred. We also benchmark write energy and speed performances of SOT-MRAM cells using several existing SOT materials, such as Pt, β -W, and Bi x Se (1−x) based on the established framework. This work will provide essential guidelines for SOT-MRAM materials and device research in the future.