Abstract
As spin-orbit-torque magnetic random-access memory (SOT-MRAM) is gathering great interest as the next-generation low-power and high-speed on-chip cache memory applications, it is critical to analyze the magnetic tunnel junction (MTJ) properties needed to achieve sub-ns, and ~fJ write operation when integrated with CMOS access transistors. In this paper, a 2T-1MTJ cell-level modeling framework for in-plane type Y SOT-MRAM suggests that high spin Hall conductivity and moderate SOT material sheet resistance are preferred. We benchmark write energy and speed performances of type Y SOT cells based on various SOT materials experimentally reported in the literature, including heavy metals, topological insulators and semimetals. We then carry out detailed benchmarking of SOT material Pt, beta-W, and BixSe(1-x) with different thickness and resistivity. We further discuss how our 2T-1MTJ model can be expanded to analyze other variations of SOT-MRAM, including perpendicular (type Z) and type X SOT-MRAM, two-terminal SOT-MRAM, as well as spin-transfer-torque (STT) and voltage-controlled magnetic anisotropy (VCMA)-assisted SOT-MRAM. This work will provide essential guidelines for SOT-MRAM materials, devices, and circuits research in the future.
Highlights
Spin-orbit-torque magnetic random-access memory (SOT-MRAM) is a promising candidate to achieve faster and more energy-efficient read and write operation compared with the current in-production spin-transfer-torque MRAM (STT-MRAM)
The most advanced STT-MTJ can achieve 1 ns switching with a current density of 10-20 MA/cm2 in sub-50nm perpendicular magnetic tunnel junctions (MTJs) [1], [2]
To simplify the analysis based on the single-layer SOT material/free layer (FL) model, we do not include these bilayers in this work
Summary
Spin-orbit-torque magnetic random-access memory (SOT-MRAM) is a promising candidate to achieve faster and more energy-efficient read and write operation compared with the current in-production spin-transfer-torque MRAM (STT-MRAM). Using a simplified version of this framework, we show that the write energy-delay performance of the SOT-MRAM cell depends on two critical properties of the SOT layer, i.e., the spin Hall conductivity, and sheet resistance. Based on this simplified analysis, we propose guidelines to achieve sub-ns and ∼fJ operation of SOT-MTJ. Compared with the original paper presented at the 2019 IEEE S3S Conference [16], this paper includes a new figure (Fig. 3 and Table 2) to better illustrate the switching current and energy dependence on SOT layer sheet resistance and spin Hall conductivity, as well as to benchmark the write current and energy performance of various SOT materials reported in literature. The write current and energy will be higher if driving the FinFET at maximum current
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