Material and process trends for moving from FOWLP to FOPLP

Abstract

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. The technology offers not only solutions for single chip packaging but also approaches for 3D system integration or RF suitable packaging. Mold embedding for this technology is currently done on wafer level up to 12/300 mm size. For higher productivity and therewith lower costs larger mold embedding form factors are forecasted for the near future. Besides increasing wafer sizes up to 450 mm an alternative option would be moving to panel sizes leading to Fan-out Panel Level Packaging (FOPLP). Sizes for the panel could range up to 18×24 or even larger. Increasing the embedding size does not only mean an upscaling of the existing technologies but may lead to a change from using wafer processing infrastructure to the ones used for panels. This is especially true when moving from round wafer sizes to larger rectangular panel formats. Here also new materials and processes have to be taken into account. Materials for reconfigured mold embedding as well as dielectric materials for electrical wiring redistribution are key factors for reliable packaging and proven functionality as required e.g. for RF packaging. For reconfigured mold embedding, compression mold processes are used in combination with liquid, granular or sheet compound. Within this paper the evaluation of panel level compression molding with a target form factor of 24×18/610×457 mm2 is described for different materials. As basis for the redistribution on top of the mold embedded wafer typically a liquid photo-patternable dielectric polymer material is used and applied by spin coating. For large panel sizes photo-patternable materials are still of interest, these will most likely be used as dry films. These are expected to have advantages concerning processing and cost compared to liquid dielectric materials. Hence, a dry film dielectric material has been selected and evaluated for Fan-out Wafer/Panel Level Packaging. The main criterion for the selection of the thin film polymers is the curing temperature due to the fact that the final polymerization has to be done after the deposition on the molded wafer. Standard PIs and PBOs can therefore not be used because temperatures above 250 °C would damage the molding material. BCB-type materials are below this temperature limit, with cure temperatures as low as 200°C, making them ideal candidates for FOWLP. In addition the electrical properties are paving the way to RF applications. However, regarding the RF performance the inhomogeneous material mix of the package can be a critical issue, because of complex wave propagation phenomena. In order to obtain a proper design an assessment of the RF properties is therefore essential. For material and process evaluation a test vehicle has been designed with focus on material and process evaluation as well as reliability testing. In addition test structures for basic RF characterization have been designed and integrated. The test structures comprise interconnect elements such as transmission lines (TML) and vias to assess the electrical performance of FOWLP packaged ICs. Single ended coplanar and differential ended transmission lines embedded into the BCB-based dry film dielectric are connected by vias with a specifically designed silicon IC. The design was done using 3D full-wave simulations. An analysis of the RF characteristics shows low insertion loss and good return loss characteristics up to frequencies of 40 GHz. In summary this paper describes material and process trends for Fan-out packaging when moving from wafer sizes to large panel formats.