Challenges and opportunities for Fan-out Panel Level Packing (FOPLP)

Abstract

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. Mold embedding for this technology is currently done on wafer level up to 12”/300 mm size. For higher productivity and therewith lower costs larger mold embedding form factors are forecasted for the near future. Following the wafer level approach then the next step will be a reconfigured wafer size of 450 mm. An alternative option would be leaving the wafer shape and moving to panel sizes leading to Fan-out Panel Level Packaging (FOPLP). Sizes for the panel could range up to 18”×24” or even larger. For reconfigured mold embedding, compression mold processes are used in combination with liquid, granular or sheet compound. As an alternative process, lamination can be also considered. Already today PCB technologies offer the potential for large area panel packaging up to 24”×18”/610 × 457 mm2 and can be applied to form a redistribution layer [RDL] for large area reconfigured wafers or panels, replacing thin film redistribution. For PCB based RDLs a resin coated copper sheet (RCC) is laminated on the reconfigured wafer or panel, respectively. Micro vias are drilled through the RCC layer to the die pads and electrically connected by Cu plating. Final process step is the etching of Cu lines using LDI techniques for maskless patterning. State of the art equipment and materials the manufacturing of structures down to 20 μm lines and spaces with a clear development trend to 10 (mi lines and spaces and hence getting close to photolithography thin film structure sizes. Using the above mentioned maskless laser direct imaging technologies (LDI) instead of photolithography have a high potential for further cost reduction with intrinsic process advantages. The LDI cost advantage is backed by LDI availability for large panel sizes, also including 450 mm wafer form factors. Based on the technology described the Fan-out Panel Level Packaging approach will be demonstrated on full 24”×18”/610 × 457 mm2 format including large area assembly, embedding and redistribution. Related technology challenges as die shift, warpage, panel handling or yield will be discussed in detail. Using maskless LDI technology real die positions could be automatically adapted to the redistribution and hence less accurate die placement can be compensated and higher die shift could be tolerated which is a big advantage when moving towards large area with acceptable yield. In summary this paper describes the technological path from wafer level embedding to 24”×18” fan-out panel level packaging technology in combination with low cost PCB based RDL processes and discusses challenges and opportunities in detail. The technology described offers a cost effective packaging solution for various application as packages for handheld consumer application or bio-medical application as sensor integration into microfluidics.