Abstract
The rapid development of multi-core system and increase of data-intensive application in recent years call for larger main memory. Traditional DRAM memory can increase its capacity by reducing the feature size of storage cell. Now further scaling of DRAM faces great challenge, and the frequent refresh operations of DRAM can bring a lot of energy consumption. As an emerging technology, Phase Change Memory (PCM) is promising to be used as main memory. It draws wide attention due to the advantages of low power consumption, high density and nonvolatility, while it incurs finite endurance and relatively long write latency. To handle the problem of write, optimizing the cache replacement policy to protect dirty cache block is an efficient way. In this paper, we construct a systematically multilevel structure, and based on it propose a novel cache replacement policy called MAC. MAC can effectively reduce write traffic to PCM memory with low hardware overhead. We conduct simulation experiments on GEM5 to evaluate the performances of MAC and other related works. The results show that MAC performs best in reducing the amount of writes (averagely 25.12%) without increasing the program execution time.
Highlights
Traditional computer storage system generally adopts multi-layer structure and uses DRAM as main memory
If we directly use Phase Change Memory (PCM) as main memory without protective measures, it can be disabled in hours
Our work mainly makes the following two contributions: 1) We analyse the essential factors of a cache replacement policy designed for systems using PCM memory, and construct a systematically multilevel structure to strictly make distinctions between cache blocks of different dirty degrees
Summary
Traditional computer storage system generally adopts multi-layer structure and uses DRAM as main memory. We propose a systematically multilevel structure considering both aspects of hit ratio and write traffic This structure makes clear distinctions between cache blocks of different dirty degrees. Our work mainly makes the following two contributions: 1) We analyse the essential factors of a cache replacement policy designed for systems using PCM memory, and construct a systematically multilevel structure to strictly make distinctions between cache blocks of different dirty degrees. This hierarchical structure considers both the aspects of write traffic and hit ratio.
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