<title>Multiprocessor architecture for machine vision</title>

Abstract

Machine vision algorithms are partitioned into three distinct levels: low level (image to image transformation), intermediate level (image to symbolic transformations) and high level (symbolic manipulation). Low level image processing requires a large amount of data manipulation which can be cost effectively processed using a linear processor array. When performing intermediate level operations, however, the linear processor array is liable to generate communications bottlenecks which reduce its efficiency. The aim of this work is to enhance the linear processor array architecture for intermediate level processing. An investigation of the matching of intermediate level algorithms to appropriate computer architectures is presented. Consequently an augmented tree-structured MIMD processor network is devised, tightly coupling the low, intermediate, and high level image processing stages. The network is realized using the Inmos Transputer. A representative selection of intermediate level algorithms are executed on the machine. The performance of the realized network is compared to several commercially available systems. As the network is increased in size, it is shown that the communications bottlenecks in the linear processor array are reduced to a negligible amount. Future enhancements to the system are finally considered, including automated object and feature recognition, and a tree structured hierarchy of Prolog processes.