Abstract
We introduce a new cell architecture for Dynamic Random Access Memory (DRAM) and embedded DRAM applications. By exploiting the Floating Body characteristics of partially depleted silicon on insulator (SOI) transistors, a capacitor-less DRAM cell structure can store and amplify the stored signal by using only a single transistor. Such a DRAM cell has a footprint two times smaller than that of standard DRAM cells and can be integrated in any CMOS process.
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