Low-voltage low-distortion sampling switch design in 22 nm FD-SOI CMOS technology

Abstract

This paper presents the design of very linear analog sampling switches implemented in 22 nm FD-SOI CMOS technology. A largely input-independent ON-resistance of NMOS switch is obtained using the bootstrapping technique. A novel NMOS bootstrapped switch is proposed that efficiently employs the back-gate terminal of the FD-SOI NMOS device to further enhance its linearity. SPICE simulations were performed for comparing the performance of the proposed sampling switch with two other conventional switch configurations designed in a 22 nm FD-SOI CMOS process with a nominal supply voltage of 0.8 V.