An Automatic Comparator Offset Calibration for High-Speed Flash ADCs in FDSOI CMOS Technology

Abstract

This paper presents an automatic comparator offset calibration scheme for designing high-speed flash analog-to-digital data converters (ADCs). It leverages the threshold voltage control capability via back-gate in FDSOI CMOS technology and thus does not require extra transistor pairs or capacitive loads, avoiding comparator speed degradation. An automatic calibration approach employing a successive approximation algorithm (SAA) is also developed. The comparator along with the calibration circuit are designed in a 28-nm FDSOI CMOS process. Simulation results show that the design achieves a resolution of 1.84 mV and a calibration range of ±58 mV with a power consumption of 440 μW under a 1V power supply.