Abstract
Body bias in UTBB FD-SOI CMOS technology provides an opportunity for circuit complexity reduction with optimized performance and power. The amplifier typically used in radio basebands is often tedious to optimize in low-voltage bulk CMOS. This paper presents a class AB amplifier with biasing circuit applied at the highly efficient back gate. Presented approach reduces circuit complexity and removes bias circuit loading from the signal path. The simulated results are carried in the 28nm FDSOI CMOS technology from STMicroelectronics, and demonstrate significant power reduction and full compensation of current and transconductance process variations through body biasing technique.
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