Low-Voltage Dual-Gate Organic Thin Film Transistors with Distinctly Placed Source and Drain

Abstract

Dual Gate Organic Thin Film Transistor (DG-OTFT) preferred device because of significantly higher performance in comparison to Single Gate Organic Thin Film Transistor (SG-OTFT). This paper presents the behavior analysis of proposed novel structures of DG-OTFT in terms of electrical parameters such as on-current, subthreshold slope, and threshold voltage. Subsequently, this research paper analyzes the impact on these performance parameters of the asymmetrically placed source and drain in DG-OTFTs. The two dimensional (2D) numerical device simulator is used to investigate the behavioral changes of three (3) different structures based on the distinct arrangements of contacts either at the top or bottom/asymmetric on active layer. High-voltage (>10 V) based DG-OTFTs have been thoroughly discussed in the recent research phase: yet a very less work has been reported on the low-voltage DG-OTFTs (<10 V) due to the fabrication challenges. Consequently, this paper also presents the low-voltage DG-OTFTs based on the fabricated devices for the three different proposed devices by using parylene film as the gate dielectric to meet the fabrication challenge. Simulation results show that the distinct placements of contacts may result in different device speed that leads to better switching speed for organic digital circuit applications.