Low-power Ternary Content Addressable Memory (TCAM) array for network applications

Abstract

A low-power Ternary Content Addressable Memory (TCAM) array using 16-transistor core memory cells is presented for network applications where the contents of the array are not updated very frequently. In the proposed array, the read and search operations are performed by the same circuit blocks resulting in the reduction of device count and area compared to conventional TCAM arrays. Total width of the devices in the proposed TCAM cell is 18% less compared to the currently available area efficient design of TCAM cells. Simulations results using a 32 nm process technology show that under the same robustness against noise, the proposed array dissipates 12% less leakage power with minimal impact on frequency of operation when compared to known design of low-power TCAM arrays.