Low-power folded tree architecture and multi-bit flip-flop merging technique for WSN nodes

Abstract

Wireless communication exhibits the highest energy consumption in wireless sensor network (WSN) nodes. Due to their limited energy supply from batteries, the low power design have become inevitable part of today's wireless devices. Power has become a burning issue in VLSI design. In modern integrated circuits, the power consumed by clocking gradually takes a dominant part. Reducing the power consumption not only enhance battery life but also avoid overheating problem. By employing a more appropriate Processing Element (PE), the power consumption is significantly reduced. In this paper the novel method for low power design is achieved by using Folded Tree Architecture (FTA) and Multi-Bit Flip-Flop Merging (MBFM) technique for on-the-node data processing in wireless sensor networks using Parallel Prefix Operations (PPO) and data locality in hardware. Besides power reduction the objective of minimizing area and delay is also considered.