A low power multi-bit flip-flop design for WSN nodes

Abstract

Wireless communication exhibits the highest energy consumption in wireless sensor networks nodes. Due to their limited energy supply from batteries, the low power VLSI designs have become inevitable part of today's wireless devices. Power has become a burning issue in VLSI design. In modern integrated circuits, the power consumed by clocking gradually takes a dominant part. Reducing the power consumption not only can enhance battery life but also can avoid the overheating problem. By employing a more appropriate processing element, the power consumption is significantly reduced. In this paper the novel method for low power design is achieved by using Multi-Bit Flip-Flop Merging (MBFM) technique for on-the-node data processing in wireless sensor networks using Parallel Prefix Operations (PPO) and data locality in hardware. Besides power reduction the objective of minimizing area and delay is also considered.