Power efficient comparator architecture for wireless sensor nodes

Abstract

Designing a low power Wireless Sensor Network (WSN) Node is highly important for getting longer lifetime. Radio transmission and data processing are energy consuming processes. No compensation can be done in the field of energy consumption in radio transmission. This paper concentrates on energy reduction in the field of On the node processing. Due to limited energy supply from batteries the node must trade communication for on the node computation. Many of the WSN data processing algorithms use parallel prefix operations as common denominator. Parallel Prefix Operations have the form of Binary Tree Architecture. Binary tree architecture uses more number of Processing Element (PE) s. Parallel Prefix operations using Binary Tree Architecture (BTA) uses more area and more power. Binary Tree Architecture can be modified in to area and power efficient Folded Tree Architecture (FTA). A Digital comparator is a hardware electronic device that has two binary inputs and determines whether one number is greater than, less than or equal to the other number. The comparators are widely used in Micro Controller Units (MCUs) of WSN nodes. This is a crucial data path element of image and signal processing architectures. By using Folded Tree Architecture Area and Power Efficient Comparator Architecture can be formed. Thus Power and Area efficient WSN node can be formed.