Low-Power Convolutional Neural Network Processor for a Face-Recognition System

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The authors propose a low-power convolutional neural network (CNN)-based face recognition system for user authentication in smart devices. The system comprises two chips: an always-on functional CMOS image sensor (CIS) for imaging and face detection (FD) and a low-power CNN processor (CNNP) for face verification (FV). A functional CIS integrated with an FD accelerator enables event-driven chip-to-chip communication for face images only when there is a face. To achieve low power consumption in FD while maintaining the memory size required for the FD processing not to exceed the on-chip memory size, the authors present two-stage FD using an analog FD unit and a digital FD unit. For the event-driven FV, the CNNP adopts dynamic voltage and frequency scaling to minimize the power consumption when the number of faces in input images changes dynamically. In addition, tensor decomposition is used to reduce a CNN's workload, and the CNNP architecture based on transpose-read SRAM (T-SRAM) allows low power consumption by reducing the local memory access. Implemented in 65-nm CMOS technology, the 3.30 3.36 mmsup2/sup functional CIS and the 4 4 mmsup2/sup CNNP consume 0.62 mW to evaluate one face at 1 frame per second and achieve 97 percent accuracy in the LFW dataset.