Abstract
In order to meet the low latency and high throughput requirements of data transmission in 5th generation (5G) New Radio (NR), it is necessary to minimize the low power encoding hardware latency on transmitter and achieve lower base station power consumption within a fixed transmission time interval (TTI). This paper investigates parallel design and implementation of 5G quasi-cyclic low-density parity-check (QC-LDPC) codes encoder. The designed QC-LDPC encoder employs a multi-channel parallel structure to obtain multiple parity check bits and thus reduce encoding latency significantly. The proposed encoder maps high parallelism encoding algorithms to a configurable circuit architecture, achieving flexibility and support for all 5G NR code length and code rate. The experimental results show that under the 800 MHz system frequency, the achieved data throughput ranges from 62 to 257.9 Gbps, and the maximum code length encoding time under base graph 1 (BG1) is only 33.75 ns, which is the critical encoding time of our proposed encoder. Finally, our proposed encoder was synthesized on SMIC 28 nm CMOS technology; the result confirmed the effectiveness and feasibility of our design.
Highlights
LDPC codes was determined as the 5th generation (5G) New Radio (NR) data channel coding scheme at the 2016 3GPP Conference [1]
The computing latency of 8428 bits inputs is only 33 clocks.The results demonstrate that the cyclic redundancy check (CRC) calculation module is a suitable design for the overall encoder, and its high parallelism satisfies the fast CRC calculation and maintains a low hardware complexity
Reference [19] proposed a 5G quasi-cyclic low-density parity-check (QC-LDPC) parallel encoding algorithm based on an improved RU method
Summary
LDPC codes was determined as the 5G NR data channel coding scheme at the 2016 3GPP Conference [1]. The research on implementation of 5G LDPC codes is gradually increasing. For the implementation of the encoder, if the algorithm of multiplying the generator matrix G is directly used, the data storage and computational complexity is quadratic in the code length. To address this issue, a simplified algorithm (RU method) is proposed in [6] by transforming the sparse parity check matrix H into an approximate lower triangular form to quickly calculate the parity bits. Through the structural design of the LDPC codes, a quasi-cyclic structure was proposed to greatly reduce the complexity of encoding and the utilization of storage resources
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