Abstract
The BCH codes are widely used as Error Correcting Code (ECC) schemes for NAND Flash Memories. There have been strong demands to implement NAND Flash controller having low cost, low power and high throughput. We focus on BCH implementation since it has the largest portion in the controller. In this paper, we configure the 3-stage pipelined BCH decoder: syndrome computation, Berlekamp-Massey algorithm and Chien search. We implement BCH decoder supporting 800MB/s using the pipelined structure and the early termination method.
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