Ultra-fast-scalable BCH decoder with efficient-Extended Fast Chien Search

Abstract

In this paper, we introduced new methods in implementing ultra-fast-efficient BCH decoder that frequently used in many applications. A Reformulated inversionless-Berlekamp-Massey algorithm is adopted in order to eliminate the finite-field inverter and to reduce the hardware complexity. Furthermore, we proposed a Direct reformulated-inversionless Berlekamp-Massey algorithm (DriBM). While in the Chien Search stage, the Constant-Factor Multiplication-Free Matrix transform is also introduced to avoid expensiveness which significantly reduce the area and critical path. Moreover, we also developed Extended Fast Chien Search algorithm which significantly reduce computation complexity and the area by nearly 33% compared to Constant-Factor MFTM. Using our proposed design, we design a BCH(15,7) decoder which can reach speed up to 2.2 GHz with total area of is 8170µm2 using 0.18µm CMOS standard cell technology. The merits of the proposed algorithms and architecture are very efficient and fast. The implementation of the proposed BCH decoder architecture is also scalable to higher n block lengths and t number of correctable error, by using the same concept as we design BCH(63,51) using the same concept as BCH(15,7). In addition to the parallel BCH Decoder, we also design an area efficient parallel GF multiplier and squarer which minimized the number of logic gates. This design has been implemented and verified on Altera DE2 FPGA using codeword with various error positions and weight (0–2 guaranteed error correction). Due to its low complexity, it is suitable for VLSI implementation and also provide excellent tradeoffs between the correcting capacity, speed and area penalties.