Abstract
BCH code for correcting distributive errors has been widely used in Nand Flashes with data-based mobile systems around the world, and its decoding process is often followed by Chien search, which calculates the roots of a polynomial in finite fields by substitution and testing. Usually, BCH decoding can be accelerated by parallel syndrome computation and Chien search. In the past years the parallel Chien search circuit has been optimized to the extent that most of its area overhead in the past architecture has been reduced, which makes the other affiliated circuits significant. In this work, the error correction logics after Chien search is optimized by a three staged and group sorted circuit, in which the memory units to record error addresses are greatly saved. Synthesis results demonstrate that the proposal further compresses the area overhead for Chien search.
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