Abstract
This paper proposes a new decoding algorithm and its decoder architecture to completely remove the parallel Chien search in double error correcting (DEC) BCH decoders. The proposed algorithm called search-less decoding utilizes a quadratic formula to efficiently compute the roots of an error-location polynomial in the finite field. Since the parallel Chien search block dominates the overall complexity of a conventional DEC BCH decoder, the proposed algorithm is effective in mitigating the hardware complexity. Furthermore, a search-less (44, 32, 2) BCH decoder architecture is proposed for fault-tolerant embedded systems. Compared to the conventional decoder associated with 16-parallel Chien search, the proposed decoder decreases the hardware complexity by 51% without sacrificing the decoding throughput.
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