Low voltage low power CMOS four-quadrant analog multiplier for neural network applications

Abstract

A new low power CMOS four quadrant analog multiplier based on the operation of MOS transistors in linear region is presented. The simulated performances prove that it is possible to achieve an high input to supply ratio without a considerable amount of biasing current. Unlike almost all other designs of four quadrant multiplier in literature, this circuit allows a very low power dissipation (6 /spl mu/W for cell) using both low biasing current (4 /spl mu/A) and a 1.5 V supply. These properties make this circuit very suitable for ANN applications as a precise weighting synapse and for low power analog signal processing for portable applications. The circuit achieves an high linearity (less than 40 dB of Vina/b=1.5 Vpp@200 kHz) and a small area occupied (94 /spl mu/m/spl times/88 /spl mu/m with bias section included).