Abstract
A new CMOS four quadrant analog multiplier based on the operation of MOS transistor in the subthreshold region is presented. The circuit allows a very low power dissipation and achieves a wide input linear range by decreasing the ratio of transconductance to bias current. The transconductance reduction is obtained by a combination of four techniques: well inputs, source degeneration, gate degeneration and bump linearization. The multiplier has been implemented in a 1.2 /spl mu/m n-well CMOS process. Experimental results show that the linear range with respect to both differential inputs is approximately /spl plusmn/2 V with harmonic distortion of 3% and a power consumption on the order of 1 /spl mu/W.
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